1. Field of the Invention
This invention relates to the field of integrated circuits and, more particularly, to the assignment of input/output objects to input/output banks of an integrated circuit.
2. Description of the Related Art
Modern integrated circuits are capable of supporting a variety of different input/output (I/O) standards. Examples of I/O standards can include, but are not limited to, different varieties of Gunning Transceiver Logic (GTL) signaling such as GTL, GTL_DCI, and GTLP_DCI, Low Voltage Differential Signaling LVDS25, LVCMOS25, and the like. Each of these I/O standards specifies a set of attributes such as whether a reference voltage VREF is necessary, the value of any required VREF, whether a voltage supply VCC is needed for input (VCCI) or output (VCCO), and/or the value of any required VCCI or VCCO. This listing of I/O standards and attributes is not intended to be exhaustive, but rather illustrative of the many varieties of I/O standards and corresponding attributes.
Most modern programmable logic devices (PLDs) organize I/O objects of a circuit design into a limited number of physical I/O banks (banks) on the PLD. A PLD, such as a field programmable gate array (FPGA), can include 8 banks, although this number is not definitive of every type of PLD as different PLDs can include different numbers of banks. In any case, each bank can be associated with a plurality of different I/O objects. The I/O objects that are assigned to a given bank must be configured according to compatible I/O standards. As such, the placement of I/O objects into a given bank can be said to be constrained by the organization of that bank. In illustration, some I/O standards require a specific VCCI or VCCO. A bank typically has a single VCC supply. Accordingly, only I/O objects configured according to I/O standards that have compatible VCC requirements can be assigned to the same bank. Other attributes of I/O standards serve to further restrict the set of banks to which a given I/O object can be assigned.
The I/O objects of a circuit design can be formally divided into two or more subsets based upon the main purpose and constraints applied to each I/O object. In particular, some I/O objects provide signals to the logic core objects while others feed local and global clocks in the circuit design. These objects can be classified into groups called the select I/O subsystem and the clock I/O subsystem respectively. The main purpose of such classification is to reflect that banking rules imposed on I/O objects as well as the preferences relating to the placement of I/O objects can be different for each group.
Within an FPGA, for example, clock I/O objects drive global and local clock buffers in the device. The buffers, in turn, drive special global and local clocking resources which also are referred to as the clock-spine, clock-network, low-skew network, etc. For performance reasons, the global and local clock buffers are associated with some special I/O sites, referred to as dedicated clock I/O sites. The clock I/O objects in the circuit design may only be placed on these special, dedicated clock I/O sites. All other I/O banks on the device are not permitted to be occupied by these clock I/O objects.
The placement of I/O objects, whether select I/O or clock I/O objects, is governed by a variety of other constraints as well. One type of constraint is called a range constraint. A range constraint specifies that an I/O object has to be placed within a given region or set of banks of the target device. It should be appreciated that the region or the set of banks includes a set of I/O sites on the target device. Range constraints may be imposed by users or computer aided design (CAD) tools.
Another type of constraint is called a location constraint. A location constraint specifies that an I/O object has to be placed on a specific I/O site. Location constraints typically are user imposed and stem from an external requirement relating to, for example, printed circuit board (PCB) layout. Still, locate constraints can be imposed by CAD tools for other reasons which can include performance, routability, and runtime.
Yet another type of constraint pertains to what are called “relationally placed macros” (RPMs). An RPM is a group of select I/O and/or clock I/O objects that must be assigned to an I/O bank as a whole, without separation. Splitting an RPM into different I/O banks is forbidden and usually results in an unroutable placement. An RPM integrity constraint can be associated with I/O objects that are members of an RPM to indicate this condition. RPM integrity constraints can be put into effect by users or CAD tools for reasons including, but not limited to, performance, device restrictions, routability, runtime, and I/O standards.
The task of assigning I/O objects to banks is commonly referred to as the “Select I/O placement problem”. Past techniques for solving the select I/O placement problem have relied upon heuristics to automate I/O placement. One heuristic-based approach utilizes a combination of simulated annealing, bipartite matching, and constructive bin-packing to find a solution. Heuristic-based techniques, however, do have disadvantages. In particular, heuristic-driven techniques are not guaranteed to determine a feasible I/O placement solution despite the existence of such a solution. Further, heuristic techniques are not capable of identifying an inherently infeasible circuit design.
Another proposed solution for the I/O placement problem relies upon an Integer Linear Programming (ILP) formulation of the problem. This solution seeks to overcome the uncertainties inherent to heuristic approaches discussed above. The ILP model includes provisions for addressing voltage constraints when assigning I/O objects to physical banks. Other attributes of I/O standards, however, are not addressed. Reformulation of the ILP model to accommodate additional I/O standard attributes is not a trivial undertaking.
It would be beneficial to perform I/O placement in a manner which overcomes the limitations described above.